Development of a 0.18μm , 60V ,Power Device based on SOI LDMOS Technology
碩士 === 亞洲大學 === 資訊工程學系碩士班 === 97 === The high junction leakages, circuit latched issues, and high parasite capacitances happened in the device manufactured by junction isolation technology can be eliminated or improved if the device is manufactured by the thin SOI (Silicon-On-Insulator) technology....
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93344457966985952595 |