A 10-bit 200-MS/s Pipelined ADC with Mixed-Mode Sampling Technique
碩士 === 國立臺北科技大學 === 電機工程系研究所 === 97 === The switched-capacitor pipelined analog-to-digital converter (ADC) is the main research. This thesis includes not only the principles of ADC, but also the architectures which reduce power consumption. In this thesis, a 10-bit 200-Msample/s sampling rate pipe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/qjqwn8 |