VLSI Architecture Design of Low Complicated Parallel Turbo Decoder

• Main Authors: Kuan-Ying Lu, 盧冠穎
• Other Authors: 李文達
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/c4w626

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 97 === Excellent error correction capability and near Shannon limiting performance make turbo code to be the most important error correcting code recently. However, turbo decoder uses enormous calculations and iterations, which is difficult to be implemented and has a long decoding latency. In this thesis, we focus on parallel turbo decoder algorithms and develop a new low complicated VLSI design method for turbo decoder. With limited dividable interleaver, the number of routing multiplexers and routing complexity can be reduced efficiency. This proposed architecture can realize high order parallel turbo decoder with low complexity of multiplexer wire connecting. To verify the proposed parallel turbo decoder, we have used the Xilinx Virtex-4 FPGA to emulate the hardware architecture, and we have designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS technology. This decoder chip uses 242,876 gate counts. Chip size including I/O pad is4.014x4.014mm^2,and operation frequency is 42M Hz .