A Novel Constructive Data Compression Scheme for Low-Power Testing
碩士 === 淡江大學 === 電機工程學系碩士班 === 97 === As the design trends of very large scale integration (VLSI) circuit evolve into system-on-a-chip (SoC) design, each chip contains several reusable intellectual property (IP) cores. In order to test the chip completely, we must generate a test set for testing in a...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57004877392584365459 |