| Summary: | 碩士 === 淡江大學 === 電機工程學系碩士班 === 97 === As the design trends of very large scale integration (VLSI) circuit evolve into system-on-a-chip (SoC) design, each chip contains several reusable intellectual property (IP) cores. In order to test the chip completely, we must generate a test set for testing in advance, and store these test patterns in memory of automatic test equipment (ATE). One can imagine that test data volume increases as the integrated circuits (ICs) become complex, yet the bandwidth and memory capacity of ATE is limited. Thus, it is difficult to transmit huge test data from ATE memory to SoC. Test data compression is one of the most often used methods to deal with this problem. This technique not only reduces the volume of test data, but also shortens test application time simultaneously. In this thesis, we present two test data compression scheme for low-power testing.
In Chapter 3, a low power strategy for test data compression scheme with single scan chain is presented. In this method, we propose an efficient algorithm for scan chain reordering to deal with the power dissipation problem. In addition, we also propose a test slice difference (TSD) technique to improve test data compression. It is an efficient technique and only needs one scan cell. Consequently, hardware overhead is much lower than the cyclical scan chains (CSR) technique. In experimental results, our technique achieves high compression ratio for several large ISCAS’89 benchmark circuits. The power consumption is also better compared with other well-known compression technique.
In Chapter 4, we present a novel constructive data compression scheme that reduces both test data volume and shifting-in power for multiple scan chains. In this scheme, we only store the changed point information in ATE and use “Read Selector” to filter unnecessary encoded data. The decompression architecture contains buffers to hold the preceding data. We also propose a new algorithm to assign multiple scan chains and a new linear dependency computation method to find the hidden dependency between test slices. Experimental results show that the proposed scheme respectively outperforms previous method (selective scan slice encoding) by 57% and 77% in test data volume and power consumption on larger circuits in ISCAS’89 benchmarks.
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