A 8-BIT 50MS/s PIPELINE ANALOG TO DIGITAL CONVERTER USING LOADING FREE AND OPAMP SHARING TECHNIQUES
碩士 === 大同大學 === 電機工程學系(所) === 97 === This thesis describes A 8-bit 50M/s pipelined ADC with 1.8V supply voltage is designed and simulated with TSMC 0.18μm 1P6M CMOS models process. Many applications such as battery-powered or portable devices also require low power consumption. We proposed some meth...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31656919695689150802 |