Implementation of Finite Impulse Response Digital Filter Using Partial Reconfigurable FPGA Platform
碩士 === 元智大學 === 資訊工程學系 === 97 === This paper presents a parallel FIR(Finite Impulse Response) filter system design ,using PR(Partial Reconfiguration) to change tap of FIR ,which can achieve high flexibility , high performance ,and shorten the time of configuration. In the present thesis, we use the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75036492372523386636 |