Implementation of Finite Impulse Response Digital Filter Using Partial Reconfigurable FPGA Platform

• Main Authors: Yu-Jen Yang, 楊友仁
• Other Authors: 黃朝章
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/75036492372523386636

碩士 === 元智大學 === 資訊工程學系 === 97 === This paper presents a parallel FIR(Finite Impulse Response) filter system design ,using PR(Partial Reconfiguration) to change tap of FIR ,which can achieve high flexibility , high performance ,and shorten the time of configuration. In the present thesis, we use the Verilog HDL within Xilinx ISE 9.1i design tool to complete this architecture. After that, we use FPGA for function simulation and verify computation data. Until simulation result is correct , using Xilinx Planahead 9.2 to merge all of the architecture ,it generates full configuration circuit file and partial reconfiguration circuit file. Then, to verify by using iMPACT to download full configuration circuit file to FPGA, and download partial reconfiguration circuit file to observe the advantage of shorten time of configuration by using partial reconfiguration.