Congestion- and Energy-aware Run-time Task Mapping for Network-on-Chip Architecture
碩士 === 國立中正大學 === 資訊工程所 === 98 === With technology progress, more and more applications integrated into a single chip has increased rapidly. The conventional bus-based interconnection is no longer sufficient for supporting the large communication load in a Multiprocessor System-on-Chip (MPSoC) with...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10640191336464338932 |