Synthesis of Multi-Cycle Datapath for Variable-latency Processor
碩士 === 國立中正大學 === 資訊工程所 === 98 === Lowering supply voltages is the most straightforward and effective way to reduce power consumption. However, design variations of CMOS circuits become much more significant under low supply voltage, which makes conventional worst-case designs very inefficient. Th...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67779170540448908648 |