High-frequency and Low-jitter Half-Delay-Line All-Digital Delay Locked Loop
碩士 === 國立中正大學 === 電機工程所 === 98 === An All-Digital Delay Locked Loop operations in the high-frequency and low-jitter is presented. Currently, high-performance System-on-Chip and memory can reach multi GHz of operating frequency. Still, video decoder, like H.264, the speed of operation under this circ...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64328670713522363490 |