Power Consumption Stabilization through Resource-Constrained DFG Scheduling and Dynamic Voltage Scaling
碩士 === 長庚大學 === 資訊工程學研究所 === 98 === Power reduction is a very important issue in hardware chip design, especially when the area of a chip becomes small and small but the operations on a chip become more and more. Previous studies proposed data flow graph (DFG) scheduling algorithms to reduce a chip...
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| Format: | Others |
| Online Access: | http://ndltd.ncl.edu.tw/handle/31444463611545381932 |