A New ECO Technology for Functional Change and Removing Timing Violations
碩士 === 中原大學 === 資訊工程研究所 === 98 === In the VLSI design process, designers use spare cells when they have to make functional changes or fix timing problems. Engineering Change Order (ECO), is a technique after the placement stage, we can use the spare cells in the chip by changing the netlist informat...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39793766500248933509 |