Low Complexity and Low Power Designs on Double-Edge-Triggered Flip Flop and Prescaler
碩士 === 國立中興大學 === 電機工程學系所 === 98 === In this thesis, we proposed two novel circuit designs. The first circuit is a double-edge-triggered fip-flop. A double-edge pulse generator using pass transistor logic (PTL) is derived first. Both threshold voltage loss and poor driving capability problems common...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66222515110579005627 |