Low Complexity and Low Power Designs on Double-Edge-Triggered Flip Flop and Prescaler

• Main Authors: Shou-Wei Chen, 陳守偉
• Other Authors: Yin-Tsung Hwang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/66222515110579005627

碩士 === 國立中興大學 === 電機工程學系所 === 98 === In this thesis, we proposed two novel circuit designs. The first circuit is a double-edge-triggered fip-flop. A double-edge pulse generator using pass transistor logic (PTL) is derived first. Both threshold voltage loss and poor driving capability problems common in PTL design are successfully resolved while the circuit simplicity is kept. The proposed dual-edge pulse generator, using the signal generated by an internal node, plus the employment of an additional nMOS transistor, overcomes the shortcomings of the original design. The resultant dual-edge-triggered FF design consists of an XOR logic based pulse generator and a level sensitive latch. Circuits used in performance comparison include ep-SFF, ep-DSFF, XNOR-PFF, and the proposed design. Simulation results show that, the proposed design outperform the runner up design by 12.5% in terms of delay time and by 15% in terms of average power consumption. The second circuit is a novel divide-by-2/3 counter for low voltage and low power applicatioins. Conventional approaches of the 2/3 counter design are to embed additional logic function to the D flip-flop design to speed up the operations. In this thesis, a novel extended true single-phase clock flip-flop based low power divide-by 2/3 counter using only 13 transistors is presented. By using PTL circuit technique, the proposed design successfully reduces the total transistor-count and thus achieves better performances in various aspects. Simulation results indicate that, when compared with previous designs, as much as 12.2% savings in power and 23.4% in power-delay-product can be achieved. Both circuits were designed and simulated by using TSMC 0.18μm CMOS 1P6M process technology. The simulation conditions for the FF design are as follow: 1.8V supply voltage, 100MHz and 200MHz clock frequencies for the dual-edge- triggered and single-edge-triggered FF designs, respectively. The discrepancy in clock frequency setting is to ensure both types of design encounter the same data throughput. In average power consumption measurements, 5 commonly recognized test patterns featuring a switching probability variation ranging from 0 to 100% were adopted. The simulation conditions for the dual-modulus prescaler design include a sweep in supply voltage from 0.6V to 0.9V, and a operating frequency scan from 500MHz to 2900MHz. Besides the performance advantages over the existing designs, both of the proposed designs were also verified under the various simulation conditions, i.e., (5-Corner, operating temperature: 0 to 100 degrees C) and were proved to function properly in the face of process variations.