A 10-bit 27-MS/s Low Power SAR ADC
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed AD...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10968295848672801404 |