A 10-bit 27-MS/s Low Power SAR ADC

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed AD...

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Bibliographic Details
Main Authors:	Meng-FaYang, 楊孟法
Other Authors:	Soon-Jyh Chang
Format:	Others
Language:	en_US
Published:	2010
Online Access:	http://ndltd.ncl.edu.tw/handle/10968295848672801404

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spelling	ndltd-TW-098NCKU54421912016-04-22T04:22:57Z http://ndltd.ncl.edu.tw/handle/10968295848672801404 A 10-bit 27-MS/s Low Power SAR ADC 一個十位元每秒取樣二千七百萬次低功率逐漸趨近式類比數位轉換器 Meng-FaYang 楊孟法碩士國立成功大學電機工程學系碩博士班 98 This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed ADC. The average switching energy of the capacitor array can be reduced by 81.3% compared to the conventional switching method. The designed ADC is fabricated in TSMC 0.18-μm 1P6M CMOS technology, and occupies 0.205 mm x 0.31 mm core areas. The total chip draws 1.21 mW from 1.8-V power supply at 27-MS/s sampling rate, and the average energy consumption per conversion step is 226.2 fJ. At 20-MS/s sampling rate, the average energy consumption per conversion step is 85.7 fJ. Soon-Jyh Chang 張順志 2010 學位論文 ; thesis 72 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed ADC. The average switching energy of the capacitor array can be reduced by 81.3% compared to the conventional switching method. The designed ADC is fabricated in TSMC 0.18-μm 1P6M CMOS technology, and occupies 0.205 mm x 0.31 mm core areas. The total chip draws 1.21 mW from 1.8-V power supply at 27-MS/s sampling rate, and the average energy consumption per conversion step is 226.2 fJ. At 20-MS/s sampling rate, the average energy consumption per conversion step is 85.7 fJ.
author2	Soon-Jyh Chang
author_facet	Soon-Jyh Chang Meng-FaYang 楊孟法
author	Meng-FaYang 楊孟法
spellingShingle	Meng-FaYang 楊孟法 A 10-bit 27-MS/s Low Power SAR ADC
author_sort	Meng-FaYang
title	A 10-bit 27-MS/s Low Power SAR ADC
title_short	A 10-bit 27-MS/s Low Power SAR ADC
title_full	A 10-bit 27-MS/s Low Power SAR ADC
title_fullStr	A 10-bit 27-MS/s Low Power SAR ADC
title_full_unstemmed	A 10-bit 27-MS/s Low Power SAR ADC
title_sort	10-bit 27-ms/s low power sar adc
publishDate	2010
url	http://ndltd.ncl.edu.tw/handle/10968295848672801404
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A 10-bit 27-MS/s Low Power SAR ADC

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