Video Decoder Optimization and Parallelization for Dual-Core Embedded Systems
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === In this thesis, we focus on the algorithm optimization based on the feature of processor after the implementation of H.264/AVC decoder on dual-core embedded system. We use the dual-core embedded platform with ARM and DSP processors for example to illustrate th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84260174385467712508 |