An Embedded SRAM with DRAM Core in Standard CMOS Process
碩士 === 國立成功大學 === 電腦與通信工程研究所 === 98 === This thesis proposes a 200-MHz embedded dynamic random access memory (DRAM) that combines both the advantages of DRAM and static random access memory (SRAM). This design not only reduces the area cost but also saves the manufacturing cost. In additional, the d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67513847502568153303 |