Interface morphologic and electrical characteristic of bonded n-Si/n-GaAs

• Main Authors: Chang, Tai-Min, 張岱民
• Other Authors: Wu, Yew-Chung Sermon
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/55810986502713481713

碩士 === 國立交通大學 === 材料科學與工程系所 === 98 === The integration of III–V optical devices and Silicon attract much interest for OEICs applications. Wafer bonding can provide high quality interface for combination of these materials. During high pressure and high temperature anneal, wafer bonded by producing covalent bond at interface. However, there always exist thermal expansion mismatch between different material, great thermal stress may cause sample debond even crack after annealing. In this study, direct wafer bonding was applied to combine n-Si and n-GaAs. A simple method was used to avoid thermal stress and sample successfully bonded after high temperature anneal. The interface microstructure was investigated by transmission electrical microscopy (TEM) and I-V characteristic was also measured. The thickness of amorphous layer decrease at higher annealing temperature. The I-V measurement shows the resistance decrease with annealing temperature increase. Under forward bias ,we found unchanged turn-on voltage, due to the EL2 and Si diffusion effect. Under reverse bias, we found break-down voltage decrease with annealing temperature decrease, due to at lower temperature, thicker interface amorphous region act as trap state, lead to more leakage current path.