A Single Source Fanout Optimization Using Buffer Insertion Considering Interconnect Delay
碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 98 === As the complexity of the semiconductor device continues to explode, the EDA tool performance and IC design flows are necessary to address all nanometer issues. Buffer insertion is the state-of-the-art technology, which is used to improve the performance of t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/vyb8pu |