Study on the Novel High Speed Charge Trapping Memory Devices with Poly-Si TFTs
碩士 === 國立交通大學 === 電子研究所 === 98 === In recent years, many researchers have drawn attention to improve the program/erase efficiency of charge trapping memory devices owing to the program/erase efficiency of conventional charge trapping memory devices is lower than that of floating gate memory devi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56237471861596607387 |