Study on the Polycrystalline Silicon Thin-Film Transistors with Single Grain Boundary in the Channel for the 3D-Stacked CMOS Applications
碩士 === 國立交通大學 === 電子研究所 === 98 === In recent years, the pace of improving packing density of integrated circuits (ICs) has become slower since the device scaling has met many bottlenecks in fabrication processes, which mean that the device scaling is not an efficient approach to higher IC packin...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/79151056047598724410 |