| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 98 === In recent years, the pace of improving packing density of integrated circuits (ICs) has become slower since the device scaling has met many bottlenecks in fabrication processes, which mean that the device scaling is not an efficient approach to higher IC packing density anymore. To speed up the pace of improving IC packing density to reach the prediction of Moore’s Law, three-dimensional integrated circuits (3D-ICs) have been thought as the most promising approach. Fabricating 3D-ICs with the layer-by-layer process on a single wafer has been seen as a very promising approach to the ultimate compact 3D-ICs, as opposed to the wafer bonding process which could result in finite packing density and high wafer cost. In the layer-by-layer approach, the wafer temperature during fabrication processes should be kept low enough not to affect the performance of devices in the lower layers. As a result, the low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) technology is thought to be suitable for the layer-by-layer process to realize the dream of 3D-ICs. In this thesis, we introduced the so-called elevated channel method to control the grain growth and the location of grain boundary, which could avoid many drawbacks of the conventional excimer laser crystallization, such as random grain boundaries, narrow process window, etc. With the aid of this method, the 3D-stacked single grain boundary (3D-SSGB) TFTs with high performance and compact structure had been fabricated for the 3D-stacked CMOS applications.
In the first part, SGB polycrystalline silicon thin films fabricated by excimer laser annealing were investigated. The mechanisms of the elevated channel thin films were studied. A thick amorphous silicon region was formed in the both sides which served as the seeds for the lateral grain growth during excimer laser irradiation. As the laser energy density was controlled to completely melt the thin region in the channel and partially melt the thick region near the corner, the lateral grain growth starting from the sides of elevated channel could progress along the direction toward the center of channel region. There was only one longitudinal grain boundary in the center of the channel. Thus, a large-grain polycrystalline silicon thin film which would lead to improve the device performance was obtained. Large longitudinal grains artificially grown were observed to be about 0.7μm. Furthermore, the process window and the largest lateral grain size obtained by elevated channel method were almost the same for both the top and bottom elevated channel with different thicknesses of the separation oxide layer.
In the second part, electrical characteristics of 3D-SSGB-TFTs were also studied. For the SGB-TFTs in individual layers of 3D-SSGB-TFTs, high performance SGB-TFTs with equivalent field-effect mobility exceeding 300 cm2/V-s for n-channel devices and 140 cm2/V-s for p-channel devices have been fabricated without any hydrogenation treatment and dopant activation. The uniformity was also improved by the elevated channel method. If twenty N-type / P-type SGB-TFTs were taken into discussion, the standard deviation of equivalent field-effect mobility, subthreshold swing, and threshold voltage was smaller than 12 / 5 cm2/V-s, 0.1 / 0.2 V/decade, and 0.3 / 0.6 V, respectively. For the CMOS applications, 3D-SSGB-TFTs as a CMOS inverter showed good voltage transfer characteristics at both high and low supply voltage. Moreover, by fabricating the P-type devices in the bottom device layer of 3D-SSGB-TFTs and the separation oxide layer as thick as the gate oxide layer, the performance of bottom P-type device would be enhanced during the CMOS operation due to the double-gate effect resulted from the common-gate driving. With these proper structure arrangements, more symmetric electrical characteristics of P-type and N-type devices of the 3D-SSGB-TFTs could be successfully achieved, and thus the practicality of 3D-SSGB-TFTs as a 3D-stacked CMOS would be well improved.
To sum up, with the features such as simple process, low thermal budget, high device performance, and excellent device uniformity, the 3D-SSGB-TFT technology shows great potential in the 3D-IC applications.
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