An Ultra Low Power All Digital PLL for WidePower Supply Range
碩士 === 國立中央大學 === 電機工程研究所 === 98 === In this work, an ultra low power all digital phase locked loop(ADPLL) has wide power supply voltage range from 1.8 V to 3.6 V. ADPLL uses the proposed duty cycle corrector for 50% duty cycle. The ring oscillator and divider are used for digital controlled oscilla...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/17829112078695744387 |