Design and Implementation of 6 Gbps Half-Rate Clock and Data Recovery Circuit for SATA-III Application
碩士 === 國立中央大學 === 電機工程研究所 === 98 === According to process evolution, the volume of the data transferring between processor and memory cells is larger and larger. This progress making the conventional data bus can not deal with such huge rate. Hence, wide bandwidth transmitter and receiver become the...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/33694712893341429324 |