SSVEP Processing with Multi- Frequency and Multi-Phase Encode for Design of BCI System
碩士 === 國立中央大學 === 電機工程研究所 === 98 === This thesis mainly designs a digital signal processing circuit for electroencephalogram (EEG) of steady state visual evoked potential (SSVEP) to implement a real time brain computer interface (BCI) system. In order to reduce the cost of BCI system, it has not use...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91018168908284731289 |