Si Substrate Noise Coupling and Guard Ring Analysis
碩士 === 國立中央大學 === 電機工程研究所 === 98 === Continuous scaling of CMOS technology has resulted in chips with digital and analog circuit integrating on the same chip. However, the performance of the analog circuits will degrade due to substrate noise generated by the digital circuits. Substrate noise is an...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09239493105901219828 |