An Enhanced Yield Optimization Approach for CPPLL via Process Sensitivity Reduction
碩士 === 國立中央大學 === 電機工程研究所 === 98 === Along with the evolution of manufacturing process, the size of integrated circuits has shrunk into the nanometer scale. The process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufact...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59248681355219467242 |