Testing and Repair of Memories in 3D-SiP Chips

• Main Authors: Ting-Ju Chen, 陳亭如
• Other Authors: Jin-Fu Li
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/79093544799451011670

碩士 === 國立中央大學 === 電機工程研究所 === 98 === System-in-Package (SiP) integration technology provides a good solution for integrating components with different technologies. In an SiP, typically, various types of dies are stacked and connected with bonding wires. Among those dies, memory die is one widely used die. Furthermore, different types of memory dies may be integrated in the SiP. Using external automatic test equipment (ATE) to test these memory dies in the post-packaging phase becomes very difficult, since the I/O terminals of most of these memory dies cannot be directly accessed through the I/O pins of the package. Effective test techniques for testing these memory dies in the post-packaging phase thus should be developed. Apparently, built-in self-test (BIST) technique is a good solution for testing the memory dies in SiP designs. In the first part of this thesis, a programmable BIST scheme is proposed to test the SRAMs in a System-on-Chip(SoC) die, Flash memory dies, and SDRAM dies in an SiP chip. For the testing of SDRAMs, an efficient test procedure is proposed to reduce the testing time. Also, a specific diagnosis approach is proposed to diagnose the SDRAM when it is tested in burst mode. The proposed BIST scheme has the advantages of high diagnosability, high portability, parallel test, and low test complexity. Experimental results show that the area overhead of the proposed BIST circuit for one 512K-bit SRAM and one 1M-bit SRAM in an SoC die, and one 256M-bit Flash die is only about 0.07%. In the second part of this thesis, an adaptive syndrome compression algorithm for variable-size symbols is proposed to reduce the diagnostic data exportation time and the storage requirement of ATE. Experimental results show that the area overhead of the proposed BIST circuit with the adaptive syndrome compressor for an SiP with one SoC die in which one 512K-bit SRAM and one 1M-bit SRAM are embedded, and one 256M-bit Flash memory die is only about 0.08%. In the third part of this thesis, a reconfigurable built in redundancy analyzer (ReBIRA) scheme which can provide the optimal repair efficiency using very low area cost and one test run is proposed. In addition, a level- based buffer is proposed to extract multiple-bit failure of a faulty word to support the at-speed test and redundancy analysis for word-oriented RAMs. Experimental results show that the area cost for implementing the proposed ReBIRA scheme is much lower than that of existing works.