| Summary: | 碩士 === 國立彰化師範大學 === 資訊工程學系 === 98 === ABSTRACT
As technology advances, the coupling effects on chip are more significant so that the power dissipation and the delay on bus are increasing. And, the phenomenon results in the performance of the system on chip are ineffective. Because of on-chip bus power dissipation is dominated by the switching activities on the bus, some bus encoding schemes have proposed about reducing the switching activities. But most of bus encoding schemes use huge hardware cost to encode in order to obtain less switching activities, it causes significant power dissipation to bus. So this thesis considers correlated switchings and proposes a simple and efficient encoding method compared to the conventional methods. For 8-bit bus lines, our scheme reduces the power dissipation by 56% and reduces the worst case delay by 39% compared to conventional bus-invert method. The experiments in our study are performed on 4-bit and 8-bit bus lines based on TSMC 0.35μm 2P4M Mixed Signal Process technology, and it works by using tools provided from CIC. Final, the power and delay are measured by using HSpice. To guarantee a fair comparison, the control lines are combined with data lines in the bus of our simulations, so that our experiment results are more exactly and authentically.
|
|---|
