Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立東華大學 === 電機工程學系 === 98 === In this thesis, 10-bit 50MS/s pipelined analog-to-digital converters (ADCs) are designed. The supply voltage is 3.3V. To improve the linearity of ADCs, a cascade bootstrap switch is proposed. The dynamic performance of the 10-bit pipelined ADC with a cascade boot...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92235482442958605901 |