Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立東華大學 === 電機工程學系 === 98 === In this thesis, 10-bit 50MS/s pipelined analog-to-digital converters (ADCs) are designed. The supply voltage is 3.3V. To improve the linearity of ADCs, a cascade bootstrap switch is proposed. The dynamic performance of the 10-bit pipelined ADC with a cascade boot...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92235482442958605901 |
| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 98 === In this thesis, 10-bit 50MS/s pipelined analog-to-digital converters (ADCs) are designed. The supply voltage is 3.3V. To improve the linearity of ADCs, a cascade bootstrap switch is proposed. The dynamic performance of the 10-bit pipelined ADC with a cascade bootstrap switch is better than that of the traditional one.
The 10-bit pipelined ADC architecture includes nine stages. A 1.5-bit/per stage and a 2-bit flash ADC are adopted in the last stage. To reduce the power consumption, the front-end sample and hold circuit is removed. The opamp sharing techniques are used in the first to eighth stage. Pipelined ADCs use fully differential architecture to reduce common mode noise interference.
The designed ADCs are simulated by HSPICE using TSMC 0.35
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