Silicon Intellectual Property Design and Implementation of Area-Efficient Modulo 2^n +/- 1 Multipliers
碩士 === 國立屏東商業技術學院 === 資訊科技應用研究所 === 98 === In this thesis, we have proposed reconfigurable modulo (2^n +/-1) multipliers. By adopting common circuits for summing up the partial products and a little extra control circuits, our proposed multipliers could perform modulo (2^n+1) multiplication or modul...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56256395597238163420 |