A Transition Embedded Low Power Coding Scheme For Serial Link Interface
碩士 === 國立清華大學 === 資訊工程學系 === 98 === Serial link interconnect catches lots of attention for on-chip bus design due to its advantages over multi-bit parallel interconnect in terms of crosstalk, skew, and area cost. However, serializing multi-bit parallel bus tends to increase bit transition and power...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45262264570090505998 |