SOC Test Architecture and Method for 3D ICs

• Main Authors: Lo, Chih-Yen, 駱致彥
• Other Authors: Wu, Cheng-Wen
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/82491458727179917528

博士 === 國立清華大學 === 電機工程學系 === 98 === Abstract By continuous technology scaling, the semiconductor industry has kept up with the Moore’s Law for decades to satisfy the endless demands in both functionality and performance of electronic devices. But until recently, they have to face the bottleneck of CMOS technology scaling and soaring system-on-chip (SOC) development cost. The delay and power consumption issues of global interconnects become the main barriers of further performance progress under allowable cost. By stacking dies vertically and connecting them with through-silicon-vias (TSVs), threedimensional (3D) integration solves this problem effectively. However, there are still obstacles to its commercial application. Tools and methodologies for 3D-IC testing are regarded as the number-one challenge. We focus on the problem of test integration in 3D ICs. A flexible and scalable architecture [1] supporting both pre-bond [2] and post-bond tests for core-based 3D ICs is proposed. It is named as Test Access Control System for 3D ICs (TACS-3D) [1]. In order to reduce the testing cost of the 3D IC, not only test access mechanism (TAM) but also the control signals are optimized to reduce the usage of test pins and TSVs for 3D-IC testing. For the pre-bond test in the 3D IC, it is similar to traditional SOC testing. TACS-3D inherits the advantage of our previously developed test architecture named Test Access Control System (TACS) to provide test access and related control for embedded core testing. In addition to the patterns for traditional stuck-at faults, the timing related defects are also considered in its test features. Since TACS has optimized the test pin usage by sharing the required test control signals, TACS-3D can minimize the extra pads required for finding Known-Good Dies (KGDs) in wafer probing. To highly reuse pre-bond test circuits in the post-bond test stage, an innovative linking mechanism is proposed for sharing TSVs and test pins between embedded cores in multiple layers. No matter how many layers are there in the 3D IC, only 5-bit signals are sufficient for test control. A large portion of TSVs and test pins can be reserved for data application; therefore smaller total test time is expected. In addition, integration of heterogeneous DFT methods for logic, memory, and TSV testing in the 3D IC further alleviates the congestion of test pins and TSVs for post-bond test. For logic testing, TACS-3D retains the robustness of TACS that features the IEEE 1500 Wrapper Control, hierarchical test control, at-speed test (for transition faults), functional and scan test, heterogeneous test protocols. In addition, memory built-in self-test (MBIST) is taken as examples to support BIST-based methods in TACS-3D. Furthermore, the way to support logic built-in self-test (LBIST) can be applied through our proposed low-cost testers, i.e., the HOY wireless test system. For the newly introduced defects in the bonding processes during 3D-IC construction, TACS-3D also reuses 1500 Test Wrapper to do TSV testing. All the Wrapper Boundary Register (WBR) cells of the embedded cores whose corresponding inputs (outputs) are from (to) the upper layer of the 3D IC through TSVs are reconfigured to be the Upper TSV chains. In a similar way, all of them related to the lower layer of the 3D IC through TSVs are reconfigured to be the Lower TSV Chains. These two types of scan chains are only configured during the TSV testing. All above techniques contribute to the reduction of TSVs and test pins for 3D-IC testing. A test chip composed of a Network-Security-Processor (NSP) platform with four Crypto Processors (CPs) is taken as an example. We discuss the related effects about testing when transferring design from 2D to 3D. By adopting the proposed test architecture for 3D IC, less than 0.4% test overhead increases in both area and time between 2D and 3D test cases. The experimental results also reveal up to 54% test time improvement compared with the method of direct access.