Positive and Negative Supply Sensitivity Reduction for Ring VCO Using Bi-directional Calibration Technique

• Main Authors: Wu, Po-Hsun, 吳柏勳
• Other Authors: Chang, Tsin-Yuan
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/41078825320172803930

碩士 === 國立清華大學 === 電機工程學系 === 98 === Phase-locked loop (PLL) is widely used in computer systems and communication systems. For a lot of applications, there often exist stringent requirement in timing jitter. Therefore, how to design a PLL which is tolerant to noise has become an important issue. In PLL, the design of voltage-controlled oscillator (VCO) is quite critical. For the wide operation frequency range applications, a ring VCO is usually employed in PLL. However, the oscillation frequency of ring VCO is sensitive to supply voltage noise. Therefore, any supply noise could degrade the jitter performance. If the immunity against supply noise of VCO is enhanced, the output frequency will be stabilized. Therefore, a compensation circuit can be added to a VCO for reducing the supply sensitivity. Moreover, the sensitivity of VCO is varied at different operation frequencies, even may be positive or negative. As a result, adaptive sensitivity compensation is needed for robust performance over a wide operation frequency range. We propose a bi-directional sensitivity compensation technique and a calibration technique for reducing positive and negative sensitivity of ring VCO. Besides, by using the lock detector to activate the calibration circuit automatically, an appropriate bias can be chosen to reduce the sensitivity of VCO at different operation frequencies of PLL. The proposed design is implemented in TSMC 0.18um 1P6M CMOS technology and the supply voltage is 1.8V. With a 20mV(peak-to-peak) 10MHz sinusoidal waveform noise applied to the supply voltage, the simulated peak-to-peak jitter is improved from 25.56ps to 13.7ps at 2.8GHz operation frequency. On the other hand, the simulated peak-to-peak jitter is improved from 64.85ps to 19.21ps at 1.6GHz operation frequency. The jitter is effectively reduced over operation frequency of 1GHz to 4.0GHz. The power consumption of the proposed PLL is 16.1mW at 1.4GHz. Compared with other works, the proposed design not only provides adaptive sensitivity compensation to VCO, but also effectively reduces both positive and negative sensitivity for a wide operation frequency range.