Wide Range Synchronous Mirror Delay
碩士 === 國立臺北大學 === 電機工程研究所 === 98 === Some applications, like SDRAM uses an external clock to change the internal state of the memory. The internal clock is a delayed signal of the external clock. The clock skew between the external clock and internal clock is the sum of the input buffer delay and th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28781111572808135870 |