A Closed-Loop Gain-Error Self-Calibration Technique for Pipelined ADCs

• Main Authors: Wei-Ting Shen, 沈威廷
• Other Authors: 陳信樹
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/56108445819635392262

碩士 === 臺灣大學 === 電子工程學研究所 === 98 === This thesis presents a closed-loop gain-error self-calibration technique for pipelined ADCs, and the proposed calibration method is used in a 1.2V 10-bit pipelined ADC. The proposed pipelined ADC is design in TSMC 90nm CMOS process. A two-stage operational amplifier (opamp) with low DC gain is utilized to the multiplying DACs (MDACs). The proposed gain-error self-calibration technique allows low-gain opamps used in high-precision MDACs for pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. According to the measurement results, DNL of the proposed ADC is improved from +1.73/-1 LSB to +0.77/-0.55 LSB, and INL is improved from +13.97/-14.39 LSB to +1.45/-1.03 LSB at 40MS/s. At the sampling rate of 80MS/s, for 20MHz input frequency, the SNDR and SFDR are 54.95 dB and 63.96 dB. At 320MS/s, the SNDR and SFDR are reduced to 53.43 dB and 61.80 dB for 40MHz input. The power consumption is 47.2mW at the conversion rate of 320MS/s. The chip with pads occupies 0.86mm2.