A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops
碩士 === 臺灣大學 === 電子工程學研究所 === 98 === This thesis presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected pha...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87074750177788815385 |