Design and Implementation of High-speed and Low-jitter Delay-locked Loops
碩士 === 臺灣大學 === 電子工程學研究所 === 98 === With the evolution and scaling down of CMOS technologies, the demand for high-speed and high integration density VLSI system has recently grown exponentially. Hence, this thesis illustrates the implementation of the high speed delay-locked loops (DLLs). However, t...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2010
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Online Access: | http://ndltd.ncl.edu.tw/handle/03507105702397387845 |