Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop
碩士 === 臺灣大學 === 電子工程學研究所 === 98 === This thesis describes digital implementations and applications of analog circuits for delay-locked loop (DLL) and phase-locked loop (PLL). Compared with analog DLLs and PLLs, the all-digital DLLs and all-digital PLLs have the benefits such as easy process migratio...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29732818975573400808 |