| Summary: | 碩士 === 臺灣大學 === 電子工程學研究所 === 98 === With CMOS technology scaled into 65nm and 45nm node, the NBTI (negative bias temperature instability) effect has become a major reliability problem in modern circuit systems. In order to predict the threshold voltage shift and circuit performance degradation caused by NBTI, several analytical models have been proposed, and these models are functions of numerous condition parameters. To predict threshold voltage shift, NBTI can be calculated using the analytic model. However, the circuit performance degradation cannot be estimated using the analytic model alone, but through circuit simulations, such as SPICE. In this thesis, we predict ΔVth using predictive models proposed by other papers and utilize NBTI sub-circuit model for PMOS to calculate circuit performance degradation using HSPICE. The 3DIC (three-dimensional integral circuits) has features of high transistor density and vertically stacked dies, so it has the advantage such as enhancing circuit performance and reducing cost. However, 3DIC has the potential problem of high power density, which might cause difficulty in heat conduction and thus high chip temperature. As the NBTI effect is very sensitive to local temperature, protecting Critical Gates (CGs) can thus effectively reduce the impact of NBTI. In this work, we introduce two new concepts to 3DIC design and implementation. Firstly, we propose that in 3DIC, the CGs should be placed on low temperature dies in order to mitigate NBTI effect. Then we create a floorplan of 3D quad-core four chip system based on this concept and compare to other common floorplans. We use Hotspot to simulate steady state temperature. Finally, we propose an NBTI-aware 3DIC implement flow, which can be used to implement 3DIC layout that has less impacts from NBTI.
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