| Summary: | 碩士 === 國立臺灣科技大學 === 資訊工程系 === 98 === NAND flash memory has been widely adopted as storage media in consumer electronics and portable devices due to its shock resistance, high density, low cost, low power consumption, non-volatility, and low access latency natures. It is also a good alternative for hard disk drives. NAND flash memory could be classified into Single-Level Cell (SLC) and Multi-Level Cell (MLC). SLC is the earlier design of flash memory and could store 1 bit per cell. A numerous excellent management schemes have been proposed for SLC. In recent years, MLC, which stores 2 bits per cell, has gradually replaced SLC due to its lower cost and higher density. However, MLC also brings new constraints, i.e., no partial programming and sequential page writes within a block, to the management. This paper proposes a novel mapping scheme for MLC. The goals of our research are to avoid time out by decreasing dummy page writes, to get a better response time by decreasing live page copying, and to prolong the life span of flash memory by decreasing block erasures. Our trace-driven simulation show that the proposed set-based scheme could reduce the amount of dummy page writes/live page copying/block erasures by up to 90%/52%/83%, compared with current hybrid-level mapping schemes.
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