A Power-aware Code-compression Scheme for RISC/VLIW Architecture
碩士 === 國立臺灣科技大學 === 電子工程系 === 98 === We studied the architecture of embedded computing systems from the memory power consumption point-of-view and used selective-code- compression (SCC) approach to realize our design. Based on the LZW (Lempel-Ziv-Welch) compression algorithm, we proposed a novel...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/99333342572652783073 |