The Study of Parameter Optimization of Wafer Level Chip Scale Packages in Board Level Drop Test with Taguchi's Method.
碩士 === 國立高雄大學 === 電機工程學系碩士班 === 98 === The study of the Wafer Level Chip Scale Packages（WLCSP）was carried out with reference to past experience in the laboratory and current industry standard as an effort to analyze various combinations of the multi-stages manufacturing processes of WLCSP. To find o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/41574441483512758406 |