Development of Layout and Verification Flow for 3D IC Layout
碩士 === 南台科技大學 === 電子工程系 === 98 === As requirements for IC application become complex, SOC design was the best method to integrate chip with variety of functions in the past. However, the low selectivity of process and high cost of R&D has gradually become the shortcoming of SOC design, which ser...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/04850422889795329908 |