| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 98 === As requirements for IC application become complex, SOC design was the best method to integrate chip with variety of functions in the past. However, the low selectivity of process and high cost of R&D has gradually become the shortcoming of SOC design, which seriously limited the popularization of this method. If different IC with several processes can be integrated vertically and horizontally into a whole system by 3D-IC technology, It will perform much better with a lower cost ~cite{jjtang2008}.
3D-IC connection achieves by the mutual connecting of micro-bumps through TSV. In order to integrate system, the design rules of TSV and micro-bumps, and correctness of the connection among IC layers must be verified in the IC design process before stacking physical IC. Unfortunately, there are no appropriate layouts and software can do this until now.
Here , We attempt to exploit a feasible and practical approach for 3D-IC's physical and verification based on the present 2D-IC EDA tool.
It includes align mark and dummy layer used to define the connection of each chip layer. 8 TSV -related error patterns have been developed.
The experiments results showed that, we actually used this method to a 3-Tiers / 4 IC's 3D IC systems, it can quite rapidly confirm DRC or LVS errors. To prove the efficiency of this method, we prepared 20,000 TSV test circuit to test. The experiment results show that the whole implementation process can be completed in only a few seconds.
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