A Parallel Genetic Algorithm for Floorplanning in VLSI
碩士 === 國立臺北科技大學 === 電機工程系研究所 === 98 === In the traditional integrated circuit design flow, floorplanning is performed at the earlier stage of physical design phase. Since the design cost significantly depends on the result of floorplanning, a lot of attentions and efforts have been paid on solving t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9fmz77 |