Design and Implementation on Efficient Fair Queuing of Deficit Round Robin with FPGA.
碩士 === 國立臺北科技大學 === 電力電子產業研發碩士專班 === 98 === Generally, the end-to-end communication of network is completed with microprocessor using RISC to move those packets, even though it needs large flash memory and works slowly. A FIFO is utilized to solve the numerous memories, but the transmitting speed is...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/aa7z6s |